The present invention relates to a semiconductor device and a technique for manufacturing it and, particularly, to a technique effectively applied to a semiconductor device having wirings each including a main conductive film containing copper as a primary component.
Elements of the semiconductor device are connected by, for example, a multilayer wiring structure, whereby a circuit is configured. Along with an ultra-fine structure, an embedded wiring structure has been developed as a wiring one. The embedded wiring structure is formed by, for example, embedding, by use of a Damascene technique (Single-Damascene technique and Dual-Damascene technique), wiring materials in wiring openings such as wiring grooves and holes formed in an insulating film.
Japanese patent Laid-open No. 2002-43419 discloses a technique in which a 50 nm thick P-SiC film as a Cu atom diffusion preventing layer is formed on a Cu layer as an underlying wiring, and a low dielectric constant layer as an interlayer insulating film is formed on the P-SiC film.
Japanese Patent Laid-open No. 2002-270691 discloses a technique in which, after a copper wiring is formed, a 5 to 50 nm thick insulating barrier film made of silica carbide (SiC), silica nitride (SiN) and a mixture (SiCN) thereof, etc. is formed on a plane formed by a CMP method.
Also in Non-patent Document 1, there is described a technique for using, as a barrier dielectric, a two-layer dielectric comprising a lower α-SiC film and a upper α-SiCN film.
[Non-patent Document 1]: C. C. Chiang, M. C. Chen, Z. C. Wu, L. J. Li, S. M. Jang, C. H. Yu, M. S. Liang, TDDB Reliability Improvement in Cu Damascene by using a Bilayer-Structured PECVD SiC Dielectric Barrier, “2002 IITC (International Interconnect Technology Conference)”, (U.S.A.) IEEE, 2002, pp. 200-202